
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Requirements
Timing Requirements
Table 12:
Asynchronous READ Cycle Timing Requirements
70ns
Parameter
1
Symbol
Min
Max
Units
Notes
Address access time
t
AA
70
ns
APA
ADV# access time
Page access time
t
AADV
t
70
20
ns
ns
Address hold from ADV# HIGH
t
AVH
5
ns
BA
Address setup to ADV# HIGH
LB#/UB# access time
t AVS
t
10
70
ns
ns
LB#/UB# disable to DQ High-Z output
LB#/UB# enable to Low-Z output
Maximum CE# pulse width
t BHZ
t BLZ
t CEM
10
8
8
ns
ns
μs
4
3
2
CE# LOW to WAIT valid
t CEW
1
7.5
ns
Chip select access time
CE# LOW to ADV# HIGH
t CO
t CVS
10
70
ns
ns
Chip disable to DQ and WAIT High-Z output
Chip enable to Low-Z output
Output enable to valid output
Output hold from address change
Output disable to DQ High-Z output
Output enable to Low-Z output
Page cycle time
READ cycle time
ADV# pulse width LOW
ADV# pulse width HIGH
t HZ
t LZ
t OE
t OH
t OHZ
t OLZ
t PC
t RC
t VP
t VPH
10
5
3
20
70
10
10
8
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
3
4
3
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
High-Z timings measure a 100mV transition from either V OH or V OL toward V CC Q/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low-
Z timings measure a 100mV transition away from the High-Z (V CC Q/2) level toward either
V OH or V OL .
4. Page mode enabled only.
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16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
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